PCI接口完整引角定义原理图
PCI接口完整引角定义原理图 谢谢楼主, 謝謝分享謝謝分享 谢谢！！！！！！！！！ 非常感谢！ 非常感谢！！！我一直在想电脑主板的PCI槽定义是不是和 PCI Specification里面的一样。 我看了，是一样的！！
不过楼主发的PCI卡只用了124个脚，124脚是miniPCI的type III。但是图的引脚定义确实和PCI相同而不同于miniPCI。我还是不懂，好好学习了。
另外附上specification的资料吧
Pinout
PCI Universal Card 32/64 bit
----------------------------------------------------------------
| PCI Component Side (side B) |
| |
| |
| optional |
| ____ mandatory 32-bit pins 64-bit pins_____|
|___| |||||||--|||||||||||||||||--|||||||--||||||||||||||
^ ^^ ^^ ^^ ^
b01 b11b14 b49b52 b62b63 b94
PCI 5V Card 32/64 bit
| optional |
| ____ mandatory 32-bit pins 64-bit pins_____|
|___| ||||||||||||||||||||||||||--|||||||--||||||||||||||
PCI 3.3V Card 32/64 bit
| optional |
| ____ mandatory 32-bit pins 64-bit pins_____|
|___| |||||||--||||||||||||||||||||||||||--||||||||||||||
98+22 PIN EDGE CONNECTOR at the computer.
Pin+5V+3.3VUniversalDescription
A1TRST Test Logic Reset
A2+12V +12 VDC
A3TMS Test Mde Select
A4TDI Test Data Input
A5+5V +5 VDC
A6INTA Interrupt A
A7INTC Interrupt C
A8+5V +5 VDC
A9RESV01 Reserved VDC
A10+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)
A11RESV03 Reserved VDC
A12GND03(OPEN)(OPEN)Ground or Open (Key)
A13GND05(OPEN)(OPEN)Ground or Open (Key)
A14RESV05 Reserved VDC
A15RESET Reset
A16+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)
A17GNT Grant PCI use
A18GND08 Ground
A19RESV06 Reserved VDC
A20AD30 Address/Data 30
A21+3.3V01 +3.3 VDC
A22AD28 Address/Data 28
A23AD26 Address/Data 26
A24GND10 Ground
A25AD24 Address/Data 24
A26IDSEL Initialization Device Select
A27+3.3V03 +3.3 VDC
A28AD22 Address/Data 22
A29AD20 Address/Data 20
A30GND12 Ground
A31AD18 Address/Data 18
A32AD16 Address/Data 16
A33+3.3V05 +3.3 VDC
A34FRAME Address or Data phase
A35GND14 Ground
A36TRDY Target Ready
A37GND15 Ground
A38STOP Stop Transfer Cycle
A39+3.3V07 +3.3 VDC
A40SDONE Snoop Done
A41SBO Snoop Backoff
A42GND17 Ground
A43PAR Parity
A44AD15 Address/Data 15
A45+3.3V10 +3.3 VDC
A46AD13 Address/Data 13
A47AD11 Address/Data 11
A48GND19 Ground
A49AD9 Address/Data 9
A52C/BE0 Command, Byte Enable 0
A53+3.3V11 +3.3 VDC
A54AD6 Address/Data 6
A55AD4 Address/Data 4
A56GND21 Ground
A57AD2 Address/Data 2
A58AD0 Address/Data 0
A59+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)
A60REQ64 Request 64 bit ???
A61VCC11 +5 VDC
A62VCC13 +5 VDC
A63GND Ground
A64C/BE# Command, Byte Enable 7
A65C/BE# Command, Byte Enable 5
A66+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)
A67PAR64 Parity 64 ???
A68AD62 Address/Data 62
A69GND Ground
A70AD60 Address/Data 60
A71AD58 Address/Data 58
A72GND Ground
A73AD56 Address/Data 56
A74AD54 Address/Data 54
A75+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)
A76AD52 Address/Data 52
A77AD50 Address/Data 50
A78GND Ground
A79AD48 Address/Data 48
A80AD46 Address/Data 46
A81GND Ground
A82AD44 Address/Data 44
A83AD42 Address/Data 42
A84+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)
A85AD40 Address/Data 40
A86AD38 Address/Data 38
A87GND Ground
A88AD36 Address/Data 36
A89AD34 Address/Data 34
A90GND Ground
A91AD32 Address/Data 32
A92RES Reserved
A93GND Ground
A94RES Reserved
B1-12V -12 VDC
B2TCK Test Clock
B3GND Ground
B4TDO Test Data Output
B5+5V +5 VDC
B6+5V +5 VDC
B7INTB Interrupt B
B8INTD Interrupt D
B9PRSNT1 Reserved
B10RES +V I/O (+5 V or +3.3 V)
B11PRSNT2 ??
B12GND(OPEN)(OPEN)Ground or Open (Key)
B13GND(OPEN)(OPEN)Ground or Open (Key)
B14RES Reserved VDC
B15GND Reset
B16CLK Clock
B17GND Ground
B18REQ Request
B19+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)
B20AD31 Address/Data 31
B21AD29 Address/Data 29
B22GND Ground
B23AD27 Address/Data 27
B24AD25 Address/Data 25
B25+3.3V +3.3VDC
B26C/BE3 Command, Byte Enable 3
B27AD23 Address/Data 23
B28GND Ground
B29AD21 Address/Data 21
B30AD19 Address/Data 19
B31+3.3V +3.3 VDC
B32AD17 Address/Data 17
B33C/BE2 Command, Byte Enable 2
B34GND13 Ground
B35IRDY Initiator Ready
B36+3.3V06 +3.3 VDC
B37DEVSEL Device Select
B38GND16 Ground
B39LOCK Lock bus
B40PERR Parity Error
B41+3.3V08 +3.3 VDC
B42SERR System Error
B43+3.3V09 +3.3 VDC
B44C/BE1 Command, Byte Enable 1
B45AD14 Address/Data 14
B46GND18 Ground
B47AD12 Address/Data 12
B48AD10 Address/Data 10
B49GND20 Ground
B50(OPEN)GND(OPEN)Ground or Open (Key)
B51(OPEN)GND(OPEN)Ground or Open (Key)
B52AD8 Address/Data 8
B53AD7 Address/Data 7
B54+3.3V12 +3.3 VDC
B55AD5 Address/Data 5
B56AD3 Address/Data 3
B57GND22 Ground
B58AD1 Address/Data 1
B59VCC08 +5 VDC
B60ACK64 Acknowledge 64 bit ???
B61VCC10 +5 VDC
B62VCC12 +5 VDC
B63RES Reserved
B64GND Ground
B65C/BE# Command, Byte Enable 6
B66C/BE# Command, Byte Enable 4
B67GND Ground
B68AD63 Address/Data 63
B69AD61 Address/Data 61
B70+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)
B71AD59 Address/Data 59
B72AD57 Address/Data 57
B73GND Ground
B74AD55 Address/Data 55
B75AD53 Address/Data 53
B76GND Ground
B77AD51 Address/Data 51
B78AD49 Address/Data 49
B79+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)
B80AD47 Address/Data 47
B81AD45 Address/Data 45
B82GND Ground
B83AD43 Address/Data 43
B84AD41 Address/Data 41
B85GND Ground
B86AD39 Address/Data 39
B87AD37 Address/Data 37
B88+5V+3.3VSignal Rail+V I/O (+5 V or +3.3 V)
B89AD35 Address/Data 35
B90AD33 Address/Data 33
B91GND Ground
B92RES Reserved
B93RES Reserved
B94GND Ground
Notes: Pin 63-94 exists only on 64 bit PCI implementations.
+V I/O is 3.3V on 3.3V boards, 5V on 5V boards, and define signal rails on the Universal board. 收下了，说不定什么时候能用到呢 收下了，谢谢Ｑ！！！
谢谢。。。。。。。。。